While developing and introducing new technologies (ex. FDSOI 10nm CMOS), design rules (DRM) are the guidelines used to ensure that a chip design can be reliably fabricated. These rules govern the physical dimensions and spacing of various features used by the designer in the chip layout. They translate both device electrical constraints and manufacturing processes constraints. Among them, lithography and patterning processes are critical step in defining the intricate structures and features on a semiconductor wafer. The most efficient design rules can only be obtained from a co-optimization merging design and lithography constraints.
The objective of this research work is to demonstrate that the use of a digital lithography twin can improve the performance of CMOS by co-optimization of design and lithography (DTCO).

Starting from specific use cases for FDSOI 10nm CMOS technologies, and using advanced lithography simulation tools, the candidate would :
- Develop novel characterization methods to assess lithography process capabilities (hotspot prediction).
- Assess design rules with respect to the lithography process capabilities.
- Quantify, though design rules, lithography impact on device performances.
- Identify significant both process and design limitations and propose paths to challenge them.

As PhD student of CEA-Leti, you will join a technology research institute dedicated to micro and nanotechnologies, within a dynamic and international research environment. You will join the Computational Patterning Laboratory with strong connections with integrated circuit design experts of CEA-Leti. You will benefit from the exceptional facilities of the institute's 300mm clean room and from state-of-the art lithography software tools.
You will be encouraged to publish your work and participate to international conferences and workshops.