General information
Organisation
The French Alternative Energies and Atomic Energy Commission (CEA) is a key player in research, development and innovation in four main areas :
• defence and security,
• nuclear energy (fission and fusion),
• technological research for industry,
• fundamental research in the physical sciences and life sciences.
Drawing on its widely acknowledged expertise, and thanks to its 16000 technicians, engineers, researchers and staff, the CEA actively participates in collaborative projects with a large number of academic and industrial partners.
The CEA is established in ten centers spread throughout France
Reference
SL-DRT-26-0586
Direction
DRT
Thesis topic details
Category
Technological challenges
Thesis topics
Development of vertical GaN power transistors gate module
Contract
Thèse
Job description
This PhD topic offers a unique opportunity to enhance your skills in GaN power devices and develop cutting-edge architectures. You’ll work alongside a multidisciplinary team specializing in material engineering, characterization, device simulation, and electrical measurements. If you’re eager to innovate, expand your knowledge, and tackle state-of-the-art challenges, this position is a valuable asset to your career!
Vertical GaN power components are highly promising for applications beyond the kV range and are therefore extensively studied worldwide. Transistors with a 'trench MOSFET' architecture have been demonstrated in the state-of-the-art with very encouraging results. The gate stack of these devices is a crucial element as it directly impacts their on-state resistance, threshold voltage, and the control signal to be applied in a power converter. The proposed study will focus on developing innovative gate stacks that can withstand high gate voltages while maintaining state-of-the-art threshold voltage and channel mobility with minimal gate dielectric trapping. The work will involve studying the impact of process parameters on electrical characteristics. Special attention will be given to optimizing the gate geometry through TCAD simulations to study how its shape impacts on-state and breakdown. Identified improvements will be integrated to the devices fabricated on our 200mm GaN power devices line. The work will take place within the power devices lab and will be supported by several ongoing projects.
University / doctoral school
Electronique, Electrotechnique, Automatique, Traitement du Signal (EEATS)
Université Grenoble Alpes
Thesis topic location
Site
Grenoble
Requester
Position start date
01/10/2026
Person to be contacted by the applicant
BUCKLEY Julien
julien.buckley@cea.fr
CEA
DRT/DCOS//LAPS
Commissariat à l’énergie atomique et aux énergies alternatives
MINATEC Campus
17 rue des martyrs
F-38054 Grenoble Cedex
FRANCE
(+33) 04 38 78 42 81
Tutor / Responsible thesis director
SALEM Bassem
bassem.salem@cea.fr
CNRS
LTM Laboratoire des Technologies de la Microélectronique (LTM) – UMR 5129 CNRS / CEA / UGA
17 Av. des Martyrs, 38054 Grenoble
04.38.78.24.55
En savoir plus
https://www.linkedin.com/in/julien-buckley-6a15784/