The security of numerical systems relies on cryptographic chains of trust starting from the hardware up to end-user applications. The root of chain of trust is called a “root of trust” and takes the form a dedicated Integrated Circuit (IC), which stores and manipulates secrets. Thanks to countermeasures, those secrets are kept safe from extraction and tampering from attackers.
Scanning Electron Microscope (SEM) probing is a well-known technique in failure analysis that allows extracting such sensitive information. Indeed, thanks to a phenomenon known as voltage contrast, SEM probing allows reading levels of transistors or metal lines. This technique was widely used in the 90s on ICs frontside, but progressively became impractical with the advance of manufacturing technologies, in particular the increasing number of metal layers. Recent research work (2023) showed that SEM-based probing was possible from the backside of the IC instead of frontside. The experiments were carried-out on a quite old manufacturing technology (135 µm). Therefore, it is now essential to characterize this threat on recent technologies, as it could compromise future root of trusts and the whole chains of trust build on top of them.
The first challenge of this PhD is to build a reliable sample preparation process allowing backside access to active regions while maintaining the device functional. The second challenge is to characterize the voltage contrast phenomenon and instrument the SEM for probing active areas. Once the technique will be mature, we will compare the effect of the manufacturing technology against those threats. The FD-SOI will be specifically analyzed for potential intrinsic benefits against SEM probing.