The security of embedded systems is nowadays a fundamental issue in many domains: IoT, Automotive, Aeronautics, among others. The physical attacks are a specific threat assuming a physical access to the target. In particular, fault injection attacks on the integrated circuits (IC) allows to disturb the system in order to retrieve secret material or to achieve a special goal such as by passing secure boot to execute malicious code. Due to their powerful capacities to defeat system security, developers must protect their system against such attack to be compliant with security standards such as Common Criteria and FIPS.

Within the context of continuous downscaling of silicon technologies, and with the transition to FD-SOI technologies, the vulnerability model of an IC must be drastically revised, from the transistor level up to the complex digital circuits one. In this PhD we propose to study the attacker model validation in the at the latter level. The objective is to contribute to the definition of a model of vulnerability after synthesis-of a RTL description of a circuit (for example a core processor) in a 22 nm FD-SOI technology. These models will contribute to define the attacker model injected as input in formal-based verification tools. The candidate will have to define a methodology to characterize with laser experiments the multilayer and heterogenous models in order to provide a quantitative analysis of their limit of validity. The methodology will be tested on ASIC realized by CEA for R&D projects allowing having a full control and knowledge of the architecture, of the design and synthesis parameters and the executed codes.