Emerging unconventional hardware technologies are essential for future Edge-AI applications, but they often suffer from variability, mismatches, and technology dispersion. These non-idealities can strongly reduce AI inference accuracy if no fine-tuning or calibration is applied. Traditional supervised fine-tuning is difficult to industrialize because it raises issues related to data confidentiality, service quality, software complexity, and hardware constraints.

This PhD project aims to develop hardware-algorithm co-design methods that avoid the need for fully supervised on-chip retraining. The main goal is to create task-agnostic, inference-level self-calibration strategies able to compensate hardware mismatches at the system level. The work will study existing adaptation methods, including weight-based, feature-based, output-based, and domain adaptation approaches.

The project will define a relevant Edge-AI application, develop a generic fine-tuning method, and validate it through low-level electrical simulations. If possible, the proposed algorithm may also be tested experimentally on a custom ASIC-based hardware setup.