The miniaturization of the electronics components involves the development of new processes. Indeed, the 193nm immersion lithography alone does not permit anymore to achieve the dimensional requirements of the most advanced technological nodes (=10nm). Since the last 10 years, multi-patterning techniques have been developed to overcome the i193nm lithography limitations. Herein, we will study the « Self-Aligned Double Patterning » (SADP) technique that divides by two the initial pitch of the lithographical patterns. This technology relies on a conformal deposition of a dielectric film (spacer) over the initial patterns (mandrel). The spacers will be then used as a mask during the pattern transfer by plasma etching. The small targeted dimensions require a perfect control of the etching processes. However, the etching steps can damage the materials used herein leading to a dimension loss. One of the main challenge will be to control the etching steps and so the plasma-induced modification in order to satisfy the specifications (dimension, profile, material consumption, etch rate, uniformity…). Besides, the goal will be also to propose new SADP approaches allowing us to generate different type of patterns in order to produce planar FDSOI transistors, which is currently little reported in literature.

The challenges of this PhD ?
To develop innovative etching processes
To explore new couple of material (spacer/mandrel) and to propose an industrial integration flow that will be validated by electrical tests
To identify the technological obstacles and to propose solutions for overcoming them
To put in place a reliable characterization protocol in order to detect the physical and chemical modifications of the materials used and to accurately measure the final patterns’ dimensions