Gallium Nitride components are very good candidates for power amplification at Millimeter Wave frequencies such as 5G (~30GHz), due to their power density and energy efficiency. However, these technologies are commonly integrated on Silicon Carbide substrates, which are thermally efficient but expensive and have small diameters. CEA-LETI's GaN/Si technology provides world-class performance in Ka band, with power densities competing with GaN/SiC technologies. These devices, fabricated on 200mm Si substrates, are compatible with Silicon clean rooms and promise greater available volumes and lower costs. Furthermore, the Silicon-like back-end levels offer possibilities for dense heterogeneous integration with digital circuits, paving the way towards heterogeneous RF Integrated Circuits (RFICs).
However, few studies exist nowadays on the degradation mechanisms tied to these specific components with CMOS-compatible process: advanced barriers, in-situ MIS gates, ohmic contacts, etc... It is mandatory to know and master these effects to qualify the technology as well as better understand the device weaknesses and limitations.
The goal of this PhD is to evaluate the parasitic memory effects as well as the transistor aging under operational conditions using DC and RF measurements, linked to the device physics. The transistors will be subjected to various electrical stress conditions to model their DC & RF degradation: trapping effects measurements (BTI, DCTS), influence of the process and gate technology (Schottky vs MIS), the electrical confinement inside the structure (GaN:C, AlGaN back-barrier, etc…). Time Dependent Dielectric Breakdown (TDDB) measurements will be made on MIS gates from DC to RF domain, to study the time to breakdown increase with input signal frequency, in a similar manner than gate dielectrics in CMOS devices. Finally, electrical stresses in DC and RF conditions (RF CW stresses) will be performed to evaluate and model the transistor degradation under operational conditions.