Ferroelectric memories of the FeRAM 1T-1C type based on HZO have the potential to replace the last levels of Cache. CEA-Leti is at the state of the art in this field at the 22nm node [1], with 1T-1C bitcells already denser than those of SRAM. In this approach, the selection transistor (1T) is a front-end transistor, and the three-dimensional ferroelectric capacitor (1C) is integrated in the back-end.

It has been shown by Micron [2] that the use of a three-dimensional back-end transistor made of polycrystalline silicon allows 1/ to densify the bitcell, 2/ to stack several levels of FeRAM, and 3/ to use the CMOS under the arrays for control logic (CMOS Under Array - CuA).

The objective of this thesis is to evaluate other types of selectors, in particular vertical amorphous oxide semiconductor field-effect transistors (AOSFETs) integrated in the back-end, for the new generations of FeRAM memories. The characteristics of these back-end transistors [3] (low Ioff, low Ion, low Vth) should offer significant advantages for the operation of FeRAM memory arrays at very low voltages (< 1V) while allowing the integration of very dense 1T-1C bitcells entirely in the back-end.

The thesis will primarily be oriented towards DTCO (Design Technology Co-Optimization) to propose dense bitcells using realistic integration schemes. It will also be able to rely on recent experimental results obtained at CEA, both on AOSFETs and on 3D ferroelectric capacitors [1], with a view to first silicon demonstrations.

[1] S. Martin et al., IEDM 2024; [2] N. Ramaswamy et al., IEDM 2023; [3] S. Deng et al., VLSI 2025