The growing demand for III-V semiconductors in high-efficiency photovoltaics, quantum photonics, and advanced imaging technologies requires innovative and cost-effective fabrication methods. This PhD project focuses on developing plasma etching processes for In-based III-V semiconductors to produce high aspect ratio (HAR) structures on large wafers from 100 to 300 mm. The research addresses two key challenges: understanding how etching process windows evolve with material loading and process conditions (physical vs. chemical dominance), and minimizing electrical degradation induced by HAR etching, which is critical for device performance.
These challenges are fundamentally linked to the low volatility of In-based etch byproducts, the need to balance kinetic and thermal energy inputs to enhance etch selectivity, and the management of etch loading effects for large-scale production. The experimental approach will leverage CEA-Leti's state-of-the-art facilities, including the Photonics platform for 2–4-inch wafer processing, which enables masking strategies (hard mask deposition, photolithography) and low-temperature (<100°C) etching. Additionally, the Si platform features a next-generation 12-inch reactor with plasma pulsing capabilities for high-temperature (>150°C) etching.
Characterization will involve SEM for etch profile analysis, XPS for surface composition, and TEM-EDX for sidewall quality assessment. Damage evaluation will be performed using near-infrared photoluminescence decay to measure minority carrier lifetime and identify recombination centers. The work aims to develop optimized HAR etching processes (aspect ratios >10, critical dimensions <1 µm) for In-based III-V materials, investigate pulsed plasma techniques to reduce etch-induced damage, and provide insights into defect formation mechanisms to guide process optimization for industrial applications.