Interconnection levels (Back-End Of Line, or BEOL) in microelectronics enable the connection of transistors to achieve the desired device functionalities. The fabrication of these levels relies on lithography and plasma etching processes. Plasma dry etching is a key technique in the manufacturing of microelectronic devices, as it allows the precise definition of structures at the nanometer scale. This process involves several major challenges, including stringent control of etch profiles, critical dimensions of the patterns, and the assurance of selectivity between different materials. Beyond these technical aspects, plasma etching also raises significant environmental concerns. Indeed, the gases used in these processes, such as fluorocarbons, are often greenhouse gases with very high global warming potential (GWP).

The objective is therefore twofold: to reduce the carbon footprint of these processes while maintaining, or even improving, the critical post-etch performance metrics, such as achieving the target critical dimensions, avoiding damage to the etched materials, preventing defect formation, and ensuring the spatial uniformity of these performances