Ferroelectric transistors (FeFETs) rely on the use of an indium-based semiconductor oxide (SCO) as the channel material. This layer, less than 10 nm thick, is sensitive to the chemical environment and temperature to which it is exposed. During FeFET integration into the BEOL (Back-End-Of-Line), it is necessary to etch dielectric layers by plasma landing on the SCO layer to create the transistor's electrical contacts. The SCO exposed to the etch and stripping plasmas can be consumed and altered, rendering the SCO contacts non-functional.
The goal of this PhD is to characterize the physico-chemical, structural and electrical properties of indium-based SCO layers exposed to different etching and stripping plasmas using XPS, XRR, XRD, AFM analyses as well as electrical tests.
In parallel, an analysis of the contamination of the contact etch reactor by indium will be carried out by XPS and TXRF, in order to evaluate plasma cleaning protocols in order to effectively remove the indium from the etch equipment, which is crucial for the manufacture of this technology in a 300mm cleanroom.